Frequency synthesizer requirements for future cellular radio systems (06-026)

Woo, Mun Kit (2006) Frequency synthesizer requirements for future cellular radio systems (06-026). [USQ Project] (Unpublished)

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Abstract

This dissertation describes the research and experimentation on the future Third Generation (3G) requirements. This project makes used of an integrated Phase Locked Loop (PLL) frequency synthesizer evaluation board from Analog Devices Pte Ltd with an operating frequency range from 2.2 GHz to 2.45 GHz. The objective of this project is to evaluate the synthesizer requirements of future 3G mobile systems. By extrapolating from existing 3G systems and conducting some researches, it is able to make an educated guess on the frequency synthesizer requirements for the future 3G mobile systems. These requirements and performance are then compared to the hardware evaluation and software simulated findings retrieved from the evaluation board and its simulation software as well as from all other designs. Finally, from the outcome of these comparisons, it is able to conclude which designs are likely to be more suitable for future 3G mobile systems. Moreover, with this project, apart from giving the student a chance to predict the requirements for future 3G system and verified them in the near future, it also helps to create a good learning experience to any students who are very new to frequency synthesizer system but very much interested in getting to know its performance and how it actually functions. For the first stage of the project, researches on both the current and future 3G requirements are carried out. At the same time, research on suitable frequency synthesizer techniques and evaluation boards are also conducted. With all the important parameters collected from the researches done for both the current and future 3G requirements, it can then be used as an input criteria in selecting a suitable PLL frequency synthesizer evaluation board from the available market for future 3G applications. Following the first stage, the second stage will includes hardware evaluation and software simulation on the suitable PLL frequency synthesizer evaluation board bought from Analog Devices Pte Ltd. However, due to some unforeseen circumstances, the hardware evaluation on the evaluation board is unable to carried out smoothly with all the important parameters required for future 3G applications measured as planned, thus another method to retrieve the values of these important parameters has been suggested. The suggested method is to replace the hardware evaluation portion by a software simulation using the simulation software provided by Analog Devices Pte Ltd. Finally, this dissertation also discusses the project constraints as well as the equipment and software limitations encountered during the whole project phase.


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Item Type: USQ Project
Refereed: No
Item Status: Live Archive
Depositing User: epEditor USQ
Faculty / Department / School: Historic - Faculty of Engineering and Surveying - Department of Electrical, Electronic and Computer Engineering
Date Deposited: 11 Oct 2007 01:03
Last Modified: 02 Jul 2013 22:43
Uncontrolled Keywords: cellular radio; phase locked loop (PLL); wideband code division multiple access (WCDMA); direct digital synthesis (DDS); frequency synthesizer
Fields of Research (FOR2008): 10 Technology > 1005 Communications Technologies > 100599 Communications Technologies not elsewhere classified
URI: http://eprints.usq.edu.au/id/eprint/2366

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