Ramesh Kumar, Nandini and Xiang, Wei and Wang, Yafeng (2010) An FPGA-based fast two-symbol processing architecture for JPEG 2000 arithmetic coding. In: ICASSP 2010: 35th International Conference on Acoustics, Speech, and Signal Processing, 14-19 Mar 2010, Dallas, TX. USA.
In this paper, a field-programmable gate array (FPGA) based enhanced architecture of the arithmetic coder is proposed, which processes two symbols per clock cycle as compared to the conventional architecture that processes only one symbol per clock. The input to the arithmetic coder is from the bit-plane coder, which generates more than two context-decision pairs per clock cycle. But due to the slow processing speed of the arithmetic coder, the overall encoding becomes slow. Hence, to overcome this bottleneck and speed up the process, a two-symbol architecture is proposed which not only doubles the throughput, but also can be operated at frequencies greater than 100 MHz. This architecture achieves a throughput of 210 Msymbols/sec and the critical path is at 9.457 ns.
|Item Type:||Conference or Workshop Item (Commonwealth Reporting Category E) (Paper)|
|Additional Information:||©2010 IEEE. Permanent restricted access to published version due to publisher's copyright restrictions.|
|Uncontrolled Keywords:||arithmetic coding; EBCOT; FPGA; JPEG 2000; two-symbol architecture; clocks|
|Depositing User:||Mrs Nandini Ramesh Kumar|
|Date Deposited:||01 Feb 2011 03:00|
|Last Modified:||16 Oct 2013 01:57|
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