An FPGA-based fast two-symbol processing architecture for JPEG 2000 arithmetic coding

Ramesh Kumar, Nandini and Xiang, Wei and Wang, Yafeng (2010) An FPGA-based fast two-symbol processing architecture for JPEG 2000 arithmetic coding. In: ICASSP 2010: 35th International Conference on Acoustics, Speech, and Signal Processing, 14-19 Mar 2010, Dallas, TX. USA.

[img]
Preview
PDF (Documentation)
Binder1.pdf

Download (1090Kb)

Abstract

In this paper, a field-programmable gate array (FPGA) based enhanced architecture of the arithmetic coder is proposed, which processes two symbols per clock cycle as compared to the conventional architecture that processes only one symbol per clock. The input to the arithmetic coder is from the bit-plane coder, which generates more than two context-decision pairs per clock cycle. But due to the slow processing speed of the arithmetic coder, the overall encoding becomes slow. Hence, to overcome this bottleneck and speed up the process, a two-symbol architecture is proposed which not only doubles the throughput, but also can be operated at frequencies greater than 100 MHz. This architecture achieves a throughput of 210 Msymbols/sec and the critical path is at 9.457 ns.


Statistics for USQ ePrint 18141
Statistics for this ePrint Item
Item Type: Conference or Workshop Item (Commonwealth Reporting Category E) (Paper)
Refereed: Yes
Item Status: Live Archive
Additional Information: ©2010 IEEE. Permanent restricted access to published version due to publisher's copyright restrictions.
Depositing User: Mrs Nandini Ramesh Kumar
Faculty / Department / School: Historic - Faculty of Engineering and Surveying - Department of Electrical, Electronic and Computer Engineering
Date Deposited: 01 Feb 2011 03:00
Last Modified: 11 Sep 2014 02:29
Uncontrolled Keywords: arithmetic coding; EBCOT; FPGA; JPEG 2000; two-symbol architecture; clocks
Fields of Research (FOR2008): 09 Engineering > 0906 Electrical and Electronic Engineering > 090609 Signal Processing
08 Information and Computing Sciences > 0804 Data Format > 080401 Coding and Information Theory
10 Technology > 1006 Computer Hardware > 100606 Processor Architectures
Socio-Economic Objective (SEO2008): E Expanding Knowledge > 97 Expanding Knowledge > 970108 Expanding Knowledge in the Information and Computing Sciences
Identification Number or DOI: doi: 10.1109/ICASSP.2010.5495418
URI: http://eprints.usq.edu.au/id/eprint/18141

Actions (login required)

View Item Archive Repository Staff Only